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for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the MAX144/max145 low-power, 12-bit analog-to- digital converters (adcs) are available in 8-pin ?ax and dip packages. both devices operate with a single +2.7v to +5.25v supply and feature a 7.4? succes- sive-approximation adc, automatic power-down, fast wake-up (2.5?), an on-chip clock, and a high-speed, 3-wire serial interface. power consumption is only 3.2mw (v dd = +3.6v) at the maximum sampling rate of 108ksps. at slower through- put rates, the automatic shutdown (0.2?) further reduces power consumption. the MAX144 provides 2-channel, single-ended opera- tion and accepts input signals from 0 to v ref . the max145 accepts pseudo-differential inputs ranging from 0 to v ref . an external clock accesses data- through the 3-wire serial interface, which is spi, qspi, and microwire-compatible. excellent dynamic performance and low power, com- bined with ease of use and small package size, make these converters ideal for battery-powered and data- acquisition applications, or for other circuits with demanding power-consumption and space require- ments. for pin-compatible 10-bit adcs, see the max157 and max159 data sheets. applications battery-powered systems instrumentation portable data logging test equipment isolated data acquisition medical instruments process-control monitoring system supervision features ? single-supply operation (+2.7v to +5.25v) ? two single-ended channels (MAX144) one pseudo-differential channel (max145) ? low power 0.9ma (108ksps, +3v supply) 100? (10ksps, +3v supply) 10? (1ksps, +3v supply) 0.2? (power-down mode) ? internal track/hold ? 108ksps sampling rate ? spi/qspi/microwire-compatible 3-wire serial interface ? space-saving 8-pin ?ax package ? pin-compatible 10-bit versions available MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin ?ax ________________________________________________________________ maxim integrated products 1 cs/shdn ref gnd 1 2 8 7 sclk dout ( ) are for max145 only ch0 (ch+) ch1 (ch-) v dd m max/dip top view 3 4 6 5 MAX144 max145 19-1387; rev 1; 6/02 part MAX144 acua MAX144bcua MAX144acpa 0? to +70? 0? to +70? 0? to +70? temp range pin-package 8 ?ax 8 ?ax 8 plastic dip * dice are specified at t a = +25?, dc parameters only. ** contact factory for availability. pin configuration ordering information spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. inl (lsb) ?.5 ? ?.5 MAX144bcpa MAX144bc/d MAX144aeua -40? to +85? 0? to +70? 0? to +70? 8 plastic dip dice* 8 ?ax ? ? ?.5 MAX144beua MAX144aepa MAX144bepa -40? to +85? -40? to +85? -40? to +85? 8 ?ax 8 plastic dip 8 plastic dip ? ?.5 ? MAX144amja MAX144bmja max145 acua 0? to +70? -55? to +125? -55? to +125? 8 cerdip** 8 cerdip** 8 ?ax ?.5 ? ?.5 max145bcua 0? to +70? 8 ?ax ? max145acpa max145bcpa max145bc/d 0? to +70? 0? to +70? 0? to +70? 8 plastic dip 8 plastic dip dice* ?.5 ? ? max145aeua max145beua max145aepa -40? to +85? -40? to +85? -40? to +85? 8 ?ax 8 ?ax 8 plastic dip ?.5 ? ?.5 max145bepa max145amja max145bmja -55? to +125? -55? to +125? -40? to +85? 8 plastic dip 8 cerdip** 8 cerdip** ? ?.5 ?
MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = +2.7v to +5.25v, v ref = 2.5v, 0.1f capacitor at ref, f sclk = 2.17mhz, 16 clocks/conversion cycle (108ksps), ch- = gnd for max145, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ch0, ch1 (ch+, ch-) to gnd ................. -0.3v to (v dd + 0.3v) ref to gnd .............................................. -0.3v to (v dd + 0.3v) digital inputs to gnd. ............................................. -0.3v to +6v dout to gnd............................................ -0.3v to (v dd + 0.3v) dout sink current ........................................................... 25ma continuous power dissipation (t a = +70?c) max (derate 4.1mw/?c above +70?c) .................... 330mw plastic dip (derate 9.09mw/?c above +70?c) ............727mw cerdip (derate 8.00mw/?c above +70?c) . .............. 640mw operating temperature ranges (t a ) MAX144/max145_c_a .......................................0?c to +70?c MAX144/max145_e_a. ...................................-40?c to +85?c MAX144/max145_m_a ................................ -55?c to +125?c storage temperature range .............................-65?c to +150?c lead temperature (soldering, 10s) .................................+300?c max14_a max14_b no missing codes over temperature conditions lsb 0.5 inl relative accuracy (note 2) bits 12 res resolution 1 lsb 0.75 dnl differential nonlinearity units min typ max symbol parameter ppm/?c 0.8 gain temperature coefficient lsb 3 lsb 3 offset error gain error lsb 0.05 channel-to-channel offset matching lsb 0.05 channel-to-channel gain matching -3db rolloff f in = 65khz, v in = 2.5vp-p (note 4) external clock, f sclk = 2.17mhz, 16 clocks/conversion cycle mhz 1.0 full-power bandwidth mhz 2.25 db -85 channel-to-channel crosstalk small-signal bandwidth s 7.4 t conv conversion time (note 5) total harmonic distortion (including 5th-order harmonic) db 70 sinad signal-to-noise plus distortion ratio db -80 thd db 80 sfdr spurious-free dynamic range internal clock mode, for data transfer only external clock mode internal clock 05 mhz 0.1 2.17 f sclk ps <50 aperture jitter serial clock frequency 57 s 2.5 t acq t/h acquisition time ns 25 aperture delay dc accuracy (note 1) dynamic specifications (f in(sine-wave) = 10khz, v in = 2.5vp-p, 108ksps, f sclk = 2.17mhz, ch- = gnd for max145) conversion rate (note 3)
MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +2.7v to +5.25v, v ref = 2.5v, 0.1f capacitor at ref, f sclk = 2.17mhz, 16 clocks/conversion cycle (108ksps), ch- = gnd for max145, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?c.) v ref = 2.5v on/off leakage current, v in = 0 to v dd k 18 25 input resistance a 100 140 v 0v dd + 50mv v ref input voltage range input current a 0.01 10 conditions shutdown ref input current a 0.01 1 multiplexer leakage current v 0v ref v in analog input voltage range pf 16 c in input capacitance units min typ max symbol parameter input leakage current i in 1 a input hysteresis v hys 0.2 v 0.2 5 a input high voltage v ih 2.0 v 3.0 input low voltage v il 0.8 v positive supply current i dd 0.9 2.0 ma three-state output capacitance c out 15 pf positive supply voltage v dd 2.7 5.25 v power-supply rejection shutdown, cs/ shdn = gnd operating mode psr 0.15 mv cs /shdn = v dd (note 8) v dd = 2.7v to 5.25v, v ref = 2.5v, full-scale input (note 9) three-state output leakage current 10 a output high voltage v oh v dd - 0.5 v output low voltage input capacitance v in = 0 or v dd c in 15 pf v ol 0.4 v 0.5 v dd 3.6v v dd > 3.6v cs /shdn = v dd i source = 0.5ma (note 8) i sink = 5ma i sink = 16ma analog inputs external reference digital inputs ( cs /shdn) and output (dout) power requirements (note 6) (note 7)
ns MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max 4 _______________________________________________________________________________________ timing characteristics (figure 7) (v dd = +2.7v to +5.25v, v ref = 2.5v, 0.1f capacitor at ref, f sclk = 2.17mhz, 16 clocks/conversion cycle (108ksps), ch- = gnd for max145, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?c.) internal clock, sclk for data transfer only (note 8) external clock internal clock, sclk for data transfer only c l = 100pf, figure 1 external clock c l = 100pf 50 ns 215 t ch 05 c l = 100pf, figure 1 external clock sclk pulse width high ns 215 conditions t cl sclk pulse width low ns 120 t tr cs /shdn rise to output disable ns 120 t dv s 2.5 t wake wake-up time cs /shdn fall to output enable ns 20 120 t do sclk fall to output data valid mhz 0.1 2.17 f sclk sclk clock frequency units min typ max symbol parameter internal clock, sclk for data transfer only (note 8) 50 ns 60 t sclks sclk to cs /shdn setup ns 60 t cs cs /shdn pulse width note 1: tested at v dd = +2.7v. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been calibrated. note 3: offset nulled. note 4: on channel is grounded; sine wave applied to off channel (MAX144 only). note 5: conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. note 6: the common-mode range for the analog inputs is from gnd to v dd (max145 only). note 7: adc performance is limited by the converter?s noise floor, typically 300vp-p. note 8: guaranteed by design. not subject to production testing. note 9: measured as v fs(2.7v) - v fs(5.25v) . note 10: sclk must remain stable during this time. (note 10)
MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max _______________________________________________________________________________________ 5 500 700 900 1100 1300 1500 2.5 3.0 3.5 4.0 4.5 5.5 5.0 supply current vs. supply voltage MAX144/5-01 supply voltage (v) supply current ( m a) v ref = v dd r l = c l = 50pf code = 101010100000 0 200 400 600 800 1000 -60 20 40 -20 0 -40 60 80 100 120 140 shutdown current vs. temperature MAX144/5-05 temperature (?) shutdown current (na) v ref = v dd 500 750 1250 1000 1500 -60 -20 0 20 40 -40 60 80 100 120 140 supply current vs. temperature MAX144/5-02 temperature (?) supply current ( m a) v ref = v dd r l = c l = 50pf code = 101010100000 0 200 400 600 800 1000 shutdown current vs. supply voltage MAX144/5-04 supply voltage (v) shutdown current (na) 2.5 3.0 3.5 4.0 4.5 5.5 5.0 v ref = v dd typical operating characteristics (v dd = +3.0v, v ref = 2.5v, 0.1? at ref, f sclk = 2.17mhz, 16 clocks/conversion cycle (108ksps), ch- = gnd for max145, t a = +25?, unless otherwise noted.) supply current vs. sampling rate MAX144/5-03 sampling rate (sps) supply current ( m a) 10,000 0.1 1 10 100 1000 0.1 100 1k 10k 1 10 100k v dd = v ref c l = 20pf code = 101010100000 0 0.2 0.4 0.6 0.8 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 offset error vs. supply voltage MAX144/5-06 supply voltage (v) offset error (lsb) 0 0.2 0.1 0.4 0.3 0.6 0.5 0.7 0.9 0.8 1.0 offset error vs. temperature MAX144/5-07 temperature (?) offset error (lsb) -60 -10 15 -35 40 65 90 115 140 -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0 0.2 0.4 0.3 0.5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 gain error vs. supply voltage MAX144/5-08 v dd (v) gain error (lsb) -0.5 -0.3 -0.4 -0.1 -0.2 0.1 0 0.2 0.4 0.3 0.5 gain error vs. temperature MAX144/5-09 gain error (lsb) temperature (?) -60 -10 15 -35 40 65 90 115 140
MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v dd = +3.0v, v ref = 2.5v, 0.1f at ref, f sclk = 2.17mhz, 16 clocks/conversion cycle (108ksps), ch- = gnd for max145, t a = +25?c, unless otherwise noted.) pin description external reference voltage input. sets the analog voltage range. bypass with a 100nf capacitor close to the device. ref 5 active-low chip-select input/active-high shutdown input. pulling cs /shdn high puts the device into shutdown with a maximum current of 5a. cs /shdn 6 serial data output. data changes state at sclk?s falling edge. high impedance when cs /shdn is high. dout 7 serial clock input. dout changes on the falling edge of sclk. sclk 8 analog and digital ground gnd 4 analog input: MAX144 = single-ended (ch1); max145 = differential (ch-) ch1 (ch-) 3 pin analog input: MAX144 = single-ended (ch0); max145 = differential (ch+) ch0 (ch+) 2 positive supply voltage, +2.7v to +5.25v v dd 1 function name -0.20 -0.10 -0.15 0 -0.05 0.05 0.10 0.15 0.20 0 1024 2048 3072 4096 integral nonlinearity vs. output code MAX144/5-10 output code inl (lsb) 0 0.1 0.2 0.3 0.4 0.5 2.5 3.5 3.0 4.0 4.5 5.0 5.5 integral nonlinearity vs. supply voltage MAX144/5-11 v dd (v) inl (lsb) 0 0.1 0.2 0.3 0.4 0.5 integral nonlinearity vs. temperature MAX144/5-12 inl (lsb) temperature (?c) -60 -10 15 -35 40 65 90 115 140 -140 -100 -120 -60 -80 -40 -20 0 20 02754 fft plot MAX144/5-13 frequency (khz) amplitude (db) v dd = +2.7v f in = 10khz f sample = 108ksps 12.0 11.0 1 10 100 effective number of bits vs. frequency 11.2 MAX144/5-14 frequency (khz) effective number of bits 11.4 11.6 11.8 v dd = +2.7v
_______________detailed description the MAX144/max145 analog-to-digital converters (adcs) use a successive-approximation conversion (sar) technique and on-chip track-and-hold (t/h) structure to convert an analog signal to a serial 12-bit digital output data stream. this flexible serial interface provides easy interface to microprocessors (ps). figure 2 shows a simplified functional diagram of the internal architecture for both the MAX144 (2 channels, single-ended) and the max145 (1 channel, pseudo-differential). analog inputs: single-ended (MAX144) and pseudo-differential (max145) the sampling architecture of the adc?s analog com- parator is illustrated in the equivalent input circuit of figure 3. in single-ended mode (MAX144), both chan- nels ch0 and ch1 are referred to gnd and can be connected to two different signal sources. following the power-on reset, the adc is set to convert ch0. after ch0 has been converted, ch1 will be converted and the conversions will continue to alternate between channels. channel switching is performed by toggling the cs /shdn pin. conversions can be performed on the same channel by toggling cs /shdn twice between conversions. if only one channel is required, ch0 and ch1 may be connected together; however, the output data will still contain the channel identification bit (before the msb). for the max145, the input channels form a single differ- ential channel pair (ch+, ch-). this configuration is pseudo-differential to the effect that only the signal at in+ is sampled. the return side in- must remain stable within 0.5lsb (0.1lsb for optimum results) with respect to gnd during a conversion. to accomplish this, connect a 0.1f capacitor from in- to gnd. during the acquisition interval, the channel selected as the positive input (in+) charges capacitor c hold . the acquisition interval spans from when cs /shdn falls to the falling edge of the second clock cycle (external clock mode) or from when cs /shdn falls to the first falling edge of sclk (internal clock mode). at the end of the acquisition interval, the t/h switch opens, retain- ing charge on c hold as a sample of the signal at in+. the conversion interval begins with the input multiplex- er switching c hold from the positive input (in+) to the negative input (in-). this unbalances node zero at the comparator?s positive input. MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max _______________________________________________________________________________________ 7 6k c l dout a) high-z to v 0h , v 0l to v 0h , and v oh to high-z 6k c l dout gnd gnd v dd b) high-z to v 0l , v 0h to v 0l , and v ol to high-z figure 1. load circuits for enable and disable time MAX144 max145 12-bit sar adc sclk ( ) are for max145 in out analog input mux (2 channel) ch0 (ch+) ch1 (ch-) ref t/h control logic sclk cs/shdn internal clock output register dout figure 2. simplified functional diagram ch0 (ch+) ch1 (ch-) ( ) are for max145 single-ended mode: ch0, ch1 = in+; gnd = in- differential-ended mode: ch+ = in+; ch- = in- r in 9k w zero ref gnd track hold comparator to sar t/h c hold 16pf input mux 12-bit capacitive dac c switch control logic MAX144 max145 figure 3. analog input channel structure
MAX144/max145 the capacitive digital-to-analog converter (dac) adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of 12-bit resolution. this action is equivalent to transferring a 16pf [(v in+ ) - (v in- )] charge from c hold to the bina- ry-weighted capacitive dac, which in turn forms a digi- tal representation of the analog input signal. track/hold (t/h) the adc?s t/h stage enters its tracking mode on the falling edge of cs /shdn. for the MAX144 (single- ended inputs), in- is connected to gnd and the con- verter samples the positive (+) input. for the max145 (pseudo-differential inputs), in- connects to the nega- tive input (-) and the difference of [(v in+ ) - (v in- )] is sampled. at the end of the conversion, the positive input connects back to in+ and c hold charges to the input signal. the time required for the t/h stage to acquire an input signal is a function of how fast its input capacitance is charged. if the input signal?s source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. the acquisition time, t acq , is the maximum time the device takes to acquire the signal, and is also the minimum time required for the signal to be acquired. calculate this with the follow- ing equation: t acq = 9(r s + r in )c in where r s is the source impedance of the input signal, r in (9k ? ) is the input resistance, and c in (16pf) is the input capacitance of the adc. source impedances below 1k ? have no significant impact on the ac perfor- mance of the MAX144/max145. higher source impedances can be used if a 0.01f capacitor is connected to the individual analog inputs. together with the input impedance, this capacitor forms an rc filter, limiting the adc?s signal bandwidth. input bandwidth the MAX144/max145 t/h stage offers a 2.25mhz small-signal and a 1mhz full-power bandwidth, which make it possible to use the parts for digitizing high- speed transients and measuring periodic signals with bandwidths exceeding the adcs sampling rate by using undersampling techniques. to avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. most aliasing problems can be fixed easily with an external resistor and a capacitor. however, if dc precision is required, it is usually best to choose a continuous or switched-capacitor filter, such as the max7410/ max7414 (figure 4). their butterworth characteristic generally provides the best compromise (with regard to rolloff and attenuation) in filter configurations, is easy to design, and provides a maximally flat passband response. analog input protection internal protection diodes, which clamp the analog input to v dd and gnd, allow each input channel to swing within gnd - 300mv to v dd + 300mv without damage. however, for accurate conversions, both inputs must not exceed v dd + 50mv or be less than gnd - 50mv. if an off-channel analog input voltage exceeds the supplies, limit the input current to 4ma. +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max 8 _______________________________________________________________________________________ shdn out 2 clk ref external reference cs/shdn dout 2 3 8 m p/ m c max7410 max7414 ch0 v dd v dd v dd gnd os gnd com 0.01 m f** 0.1 m f 470 w ** 0.01 m f ch1 in f c = 15khz 7 4 5 5 7 4 6 8 1 1 63 sclk MAX144 1.5mhz oscillator **used to attenuate switched-capacitor filter clock noise figure 4. analog input with anti-aliasing filter structure
selecting clock mode to start the conversion process on the MAX144/ max145, pull cs /shdn low. at cs /shdn?s falling edge, the part wakes up and the internal t/h enters track mode. in addition, the state of sclk at cs /shdn?s falling edge selects internal (sclk = high) or external (sclk = low) clock mode. internal clock (f sclk < 100khz or f sclk > 2.17mhz) in internal clock mode, the MAX144/max145 run from an internal, laser-trimmed oscillator to within 20% of the 2mhz specified clock rate. this releases the system microprocessor from running the sar conversion clock and allows the conversion results to be read back at the processor?s convenience, at any clock rate from 0 to 5mhz. operating the MAX144/max145 in internal clock mode is necessary for serial interfaces operating with clock frequencies lower than 100khz or greater than 2.17mhz. select internal clock mode (figure 5), by holding sclk high during a high/low transition of cs /shdn. the first sclk falling edge samples the data and initiates a conversion using the integrated on-chip oscillator. after the conversion, the oscillator shuts off and dout goes high, signaling the end of conversion (eoc). data can then be read out with sclk. external clock (f sclk = 100khz to 2.17mhz) the external clock mode (figure 6) is selected by tran- sitioning cs /shdn from high to low while sclk is low. the external clock signal not only shifts data out, but also drives the analog-to-digital conversion. the input is sampled and conversion begins on the falling edge of the second clock pulse. conversion must be com- pleted within 140s to prevent degradation in the con- version results caused by droop on the t/h capacitors. external clock mode provides the best throughput for clock frequencies between 100khz and 2.17mhz. output data format table 1 illustrates the 16-bit, serial data stream output format for both the MAX144 and max145. the first three bits are always logic high (including the eoc bit for internal clock mode), followed by the channel identi- fication (chid = 0 for ch0, chid = 1 for ch1, chid = 0 for the max145), and then 12 bits of data in msb-first format. after the last bit has been read out, additional sclk pulses will clock out trailing zeros. dout transi- tions on the falling edge of sclk. the output remains high-impedance when cs /shdn is high. MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max _______________________________________________________________________________________ 9 dout d9 d10 msb chid 1 1 eoc sampling instant high-z d8 d7 d6 d5 d4 d3 d2 d1 d0 high-z sclk 678 91011 12345 1213141516 t conv t wake (t acq ) t cs power down active active cs/shdn figure 5. internal clock mode timing dout d9 d10 msb chid sampling instant high-z d8 d7 d6 d5 d4 d3 d2 d1 d0 high-z sclk 678 91011 12345 1213141516 t wake (t acq ) t cs power down active power down active active cs/shdn figure 6. external clock mode timing
MAX144/max145 external reference an external reference is required for both the MAX144 and the max145. at ref, the dc input resistance is a minimum of 18k ? . during a conversion, a reference must be able to deliver 250a of dc load current and have an output impedance of 10 ? or less. use a 0.1f bypass capacitor for best performance. the reference input structure allows a voltage range of 0 to v dd + 50mv, although noise levels will decrease effective res- olution at lower reference voltages. automatic power-down mode whenever the MAX144/max145 are not selected ( cs /shdn = v dd ), the parts enter their shutdown mode. in shutdown all internal circuitry turns off, reduc- ing supply current to typically less than 0.2a. with an external reference stable to within 1lsb, the wake-up time is 2.5s. if the external reference is not stable with- in 1lsb, the wake-up time must be increased to allow the reference to stabilize. __________ applications information signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization error only and results directly from the adc?s resolution (n bits): snr (max) = (6.02 x n + 1.76)db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. therefore, snr is computed by taking the ratio of the rms signal to the rms noise which includes all spectral components minus the fundamental, the first five harmonics, and the dc offset. signal-to-noise plus distortion (sinad) sinad is the ratio of the fundamental input frequency?s rms amplitude to rms equivalent of all other adc out- put signals: effective number of bits (enob) enob indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc?s error consists only of quantization noise. with an input range equal to the full-scale range of the adc, the effective number of bits can be calculated as follows: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmon- ics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd- through 5th-order harmonics. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the fundamental (maximum signal component) to the rms value of the next largest spurious component, excluding dc offset. connection to standard interfaces the MAX144/max145 interface is fully compatible with spi, qspi, and microwire standard serial interfaces. if a serial interface is available, establish the cpu?s seri- al interface as master so that the cpu generates the serial clock for the MAX144/max145. select a clock fre- quency from 100khz to 2.17mhz (external clock mode). 1) use a general-purpose i/o line on the cpu to pull cs /shdn low while sclk is low. 2) wait for the minimum wake-up time (t wake ) speci- fied before activating sclk. 3) activate sclk for a minimum of 16 clock cycles. the serial data stream of three leading ones, the channel identification, and the msb of the digitized input signal begin at the first falling clock edge. dout transitions on sclk?s falling edge and is available in msb-first format. observe the sclk to thd = 20 x log v+v+v+v v 2 2 3 2 4 2 5 2 1 ? ? ? ? ? ? ? ? ? ? sinad(db) = 20 x log (noise + distortion) signal rms rms ? ? +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max 10 ______________________________________________________________________________________ table 1. serial output data stream for internal and external clock mode sclk cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 dout (internal clock) eoc 1 1 chid d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dout (external clock) 1 1 1 chid d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0
dout valid timing characteristic. data should be clocked into the p on sclk?s rising edge. 4) pull cs /shdn high at or after the 16th falling clock edge. if cs /shdn remains low, trailing zeros will be clocked out after the lsb. 5) with cs /shdn high, wait at least 60ns (t cs ) before starting a new conversion by pulling cs /shdn low. a conversion can be aborted by pulling cs /shdn high before the conversion ends; wait at least 60ns before starting a new conversion. data can be output in two 8-bit sequences or continu- ously. the bytes will contain the result of the conversion padded with three leading ones and the channel identi- fication before the msb. if the serial clock hasn?t been idled after the last lsb and cs /shdn is kept low, dout sends trailing zeros. spi and microwire interface when using spi (figure 8a) or microwire (figure 8b) interfaces, set cpol = 0 and cpha = 0. conversion begins with a falling edge on cs /shdn (figure 8c). two consecutive 8-bit readings are necessary to obtain the entire 12-bit result from the adc. dout data transi- tions on the serial clock?s falling edge and is clocked into the p on sclk?s rising edge. the first 8-bit data stream contains three leading ones, the channel identi- MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max ______________________________________________________________________________________ 11 cs/shdn sclk dout t cl t dv t ch t sclks high-z high-z t cs t do t tr figure 7. detailed serial-interface timing sequence MAX144 max145 cs/shdn sclk dout i/o sk si microwire cs/shdn sclk dout i/o sck miso v dd ss MAX144 max145 spi figure 8a. spi connections 8b. microwire connections chid d11 d10 d9 d8 1 2 3 4 5 6 7 8 9 10111213141516 d7 d6 d5 d4 d3 high-z dout* cs/shdn sclk 1st byte read 2nd byte read sampling instant *when cs/shdn is high, dout = high-z msb lsb d2 d1 d0 figure 8c. spi/microwire interface timing sequence (cpol = cpha = 0)
MAX144/max145 fication, and the first four data bits starting with the msb. the second 8-bit data stream contains the remaining bits, d7 through d0. qspi interface using the high-speed qspi interface with cpol = 0 and cpha = 0, the MAX144/max145 support a maxi- mum f sclk of 2.17mhz. the qspi circuit in figure 9a can be programmed to perform a conversion on each of the two channels for the MAX144. figure 9b shows the qspi interface timing. pic16 with ssp module and pic17 interface the MAX144/max145 are compatible with a pic16/ pic17 controller (c), using the synchronous serial-port (ssp) module. to establish spi communication, connect the controller as shown in figure 10a and configure the pic16/pic17 as system master by initializing its synchronous serial- port control register (sspcon) and synchronous serial- port status register (sspstat) to the bit patterns shown in tables 2 and 3. in spi mode, the pic16/pic17 cs allow 8 bits of data to be synchronously transmitted and received simulta- neously. two consecutive 8-bit readings (figure 10b) are necessary to obtain the entire 12-bit result from the adc. dout data transitions on the serial clock?s falling edge and is clocked into the c on sclk?s rising edge. the first 8-bit data stream contains three leading ones, the channel identification, and the first four data bits starting with the msb. the second 8-bit data stream contains the remaining bits, d7 through d0. +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max 12 ______________________________________________________________________________________ chid d11 d10 d9 d8 1 2 3 4 5 6 7 8 9 10111213141516 d7 d6 d5 d4 d3 high-z dout cs/shdn sclk sampling instant *when cs/shdn is high, dout = high-z msb lsb d2 d1 d0 figure 9b. qspi interface timing sequence (cpol = cpha = 0) cs/shdn sclk dout cs sck miso v dd ss qspi MAX144 max145 figure 9a. qspi connections table 2. detailed sspcon register contents control bit MAX144/max145 settings synchronous serial-port control register (sspcon) wcol bit7 x write collision detection bit sspov bit6 x receive overflow detect bit ckp bit4 0 clock polarity select bit. ckp = 0 for spi master mode selection. sspm2 bit2 0 sspm1 bit1 0 sspm0 bit0 1 sspm3 bit3 0 synchronous serial-port mode select bit. sets spi master mode and selects f clk = f osc / 16. sspen bit5 1 synchronous serial-port enable bit. 0: disables serial port and configures these pins as i/o port pins. 1: enables serial port and configures sck, sdo and sci pins as serial port pins. x = don?t care
layout, grounding, and bypassing for best performance, use printed circuit boards (pcbs). wire-wrap configurations are not recommend- ed, since the layout should ensure proper separation of analog and digital traces. run analog and digital lines anti-parallel to each other, and don?t lay out digital sig- nal paths underneath the adc package. use separate analog and digital pcb ground sections with only one star-point (figure 11) connecting the two ground systems (analog and digital). for lowest-noise operation, ensure the ground return to the star ground?s power supply is low impedance and as short as possible. route digital signals far away from sensitive analog and reference inputs. high-frequency noise in the power supply v dd could influence the proper operation of the adc?s fast com- parator. bypass v dd to the star ground with a network of two parallel capacitors (0.1f and 1f) located as close as possible to the power supply pin of MAX144/ max145. minimize capacitor lead length for best sup- ply-noise rejection and add an attenuation resistor (10 ? ) if the power supply is extremely noisy. MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max ______________________________________________________________________________________ 13 control bit MAX144/max145 settings synchronous serial-port status register (sspstat) smp bit7 0 spi data input sample phase. input data is sampled at the middle of the data output time. cke bit6 1 spi clock edge select bit. data will be transmitted on the rising edge of the serial clock. d/a bit5 x data address bit p bit4 x stop bit s bit3 x start bit r/w bit2 x read/write bit information ua bit1 x update address bf bit0 x buffer full status bit table 3. detailed sspstat register contents chid d11 d10 d9 d8 1 2 3 4 5 6 7 8 9 10111213141516 d7 d6 d5 d4 d3 high-z dout* cs/shdn sclk 1st byte read 2nd byte read sampling instant *when cs/shdn is high, dout = high-z msb lsb d2 d1 d0 figure 10b. spi interface timing with pic16/pic17 in master mode (cke = 1, ckp = 0, smp = 0, sspm3esspm0 = 0001) sck sdi gnd gnd i/o sclk dout cs/shdn v dd v dd MAX144 max145 pic16/17 figure 10a. spi interface connection for a pic16/pic17 controller x = don?t care
MAX144/max145 chip information transistor count: 2,058 substrate connected to gnd +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max 14 ______________________________________________________________________________________ +3v gnd +3v power supplies dgnd +3v gnd v dd digital circuitry r* = 10 w 1 m f 0.1 m f * optional filter resistor MAX144 max145 figure 11. power-supply bypassing and grounding
MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max ______________________________________________________________________________________ 15 8lumaxd.eps ________________________________________________________package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .)
MAX144/max145 +2.7v, low-power, 2-channel, 108ksps, serial 12-bit adcs in 8-pin max maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. pdipn.eps _____ _____ ________________________________package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .)

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